PDH

1. Plesiosynchronous digital hierarchy
2. Speed hierarchy
   1. DS0

Plesiosynchronous digital hierarchy

• TDM:
  • 125µs polling interval
  • manual timeslot config
• multiplexing: slow channels → fast channel
• TDM switch:
  • transpose timeslots
  • transposition matrix is static

(config)# controller e1 <INTF>
(config-controller)# channel-group <N> timeslots <LIST>

# show controllers e1

Speed hierarchy

level	US(T)	Japan	Europe(E)
0	64	64	64
1	1544	1544	2048
2	6312	6312	8448
3	44736	32064	34368
4	ø	97728	139264

• cannot be enhanced further because of async nature
• bit stuffing: insert bits (up to E1) or bytes (E3, E4) to mitigate speed difference
• DS0 cannot be unpacked from the stream, unpacking has to be ordered

DS0

• 64 kbps: 8 bit encoding with 8 kHz frequency
• analog telephony